60 mhz ccd signal processor with v- driver and precision timing generator data sheet ADDI9020 rev. spa document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 1.8 v analog/digital core integrated 12 - channel vertical driver (v - driver) 12- bit, 60 mhz analog - to - digital converter (adc) complete on - chip timing generator precision timing core with ~ 260 ps resolution correlated double sampler (cds) with variable gain 0 db to 36 db , 10- bit variable gain amplifier (vga) black level clamp with variable level control on - chip 3 v horizontal and reset gate (rg) drivers 2- phase and 4 - phase h - clock modes electronic and mechanical shutter support on - chip 1.8 v ldo on - ch ip driver for external crystal on - chip sync generator with external sync input applications high speed digital cameras general description the ADDI9020 is a complete 60 mhz front - end solution for digital still cameras and other charge - coupled device ( ccd ) imaging applications. the ADDI9020 include s the analog front end (afe), a fully programmable timing generator (tg), and a 12- channel v- driver. a precision timing ? core allows adjustment of high s peed clocks with approximately 260 ps resolution at 60 mhz op eration. the on - chip v - driver supports up to 12 channels for use with multifield ccds. the analog front end includes black level clamping, cds, vga, and a 12 - bit adc. the timing generator and v - driver provide all the necessary ccd clocks: rg, h - clocks, ve rtical clocks, sensor gate pulses, a substrate clock, and substrate bias control. the internal registers are programmed using a 3 - wire serial interface. packaged in a 7 mm 7 mm csp_bga , the ADDI9020 is specified over an operating temperature range of ?25c to +85c. functional block dia gram ADDI9020 cds vga clamp 12-bit adc sck, sl, sdata cli vref 0db to 36db horizontal drivers isatg rg h1 to h4 reft refb precision timing generator internal clocks hd vd internal registers ccdin 0db to 18db 12 hl clo gpo1 to gpo6 xsubck, xsubcnt 4 6 ldoin (3v) ldoout (1.8v) ldo reg vertica l driver subck v1 to v8 (3-level) v9 to v12 (2-level) d0 to d11 sync dclk 3 20 12 2 10643-001 figure 1. for more information about the ADDI9020, c ontact analog devices, inc. via email at: afe.ccd@analog.com
ADDI9020 data sheet rev. spa | page 2 of 2 notes ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10643f -0- 4/13(spa)
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